`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:12:11 03/24/2010 
// Design Name: 
// Module Name:    rab_internal 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module rab_internal(
    input clock,
    input scanstart_n,
	input reset,
    output regtclk,
    output tferclk,
    output adcclk
    );


reg Q2, Q1;
wire Q2_n, Q1_n, Q2_next, Q1_next;

assign Q1_n = ~Q1;
assign Q2_n = ~Q2;
assign Q1_next = Q2;
assign Q2_next = ~(Q2 & scanstart_n);

always @(posedge clock, posedge reset) begin
	if(reset) begin
	Q2 <= 1'b0;
	Q1 <= 1'b0;
	end	
	else begin
	Q2 <= Q2_next;
	Q1 <= Q1_next;
	end
end	

assign regtclk = Q2_n;
assign tferclk = ~scanstart_n;
assign adcclk = Q1_n;

endmodule
